Deep-submicron complementary metal oxide semiconductor (CMOS) is conventionally the primary technology for ultra-large scale integrated (ULSI) circuits. Over the last two decades, reduction in the size of CMOS transistors has been a principal focus of the microelectronics industry.
Transistors (e.g., MOSFETs), are often built on the top surface of a bulk substrate. The substrate is doped to form source and drain regions, and a conductive layer is provided between the source and drain regions. The conductive layer operates as a gate for the transistor; the gate controls current in a channel between the source and the drain regions.
Ultra-large-scale integrated (ULSI) circuits generally include a multitude of transistors, such as, more than one million transistors and even several million transistors that cooperate to perform various functions for an electronic component. The transistors are generally complementary metal oxide semiconductor field effect transistors (CMOSFETs) which include a gate conductor disposed between a source region and a drain region. The gate conductor is provided over a thin gate oxide material. Generally, the gate conductor can be a metal, a polysilicon, or polysilicon/germanium (SixGe(1-x)) material that controls charge carriers in a channel region between the drain and the source to turn the transistor on and off. Conventional processes typically utilize polysilicon based gate conductors because metal gate conductors are difficult to etch, are less compatible with front-end processing, and have relatively low melting points. The transistors can be N-channel MOSFETs or P-channel MOSFETs.
Generally, it is desirable to manufacture smaller transistors to increase the component density on an integrated circuit. It is also desirable to reduce the size of integrated circuit structures, such as vias, conductive lines, capacitors, resistors, isolation structures, contacts, interconnects, etc. For example, manufacturing a transistor having a reduced gate length (a reduced width of the gate conductor) can have significant benefits. Gate conductors with reduced widths can be formed more closely together, thereby increasing the transistor density on the IC. Further, gate conductors with reduced widths allow smaller transistors to be designed, thereby increasing speed and reducing power requirements for the transistors.
One issue that must be considered in fabricating integrated circuits is damage to gate structures resulting from the removal of etch masks overlying the gate structure. In conventional gate fabrication, gate structures may be produced from a polysilicon-containing material that is pre-doped with n-type (e.g., phosphorous) or p-type (e.g., boron) ions to alter the electrical characteristics of the gate. Specifically, the workfunction of the gate electrode is modulated by pre-doping polysilicon to n- or p-type, which allows formation of transistors with a predetermined threshold voltage. To form the gates, an anti-reflective coating (ARC) layer (e.g., silicon nitride (SiN), silicon oxynitride (SiON), etc.) or similar nitride-based dielectric may be patterned to form a mask for the polysilicon material. When the ARC layer is removed using a phosphoric acid (H3PO4) strip, the acid can attack exposed gate structures. Damage to the gate structures is particularly pronounced for n-type doped gates. To minimize the effects on n-type gates, a polysilicon re-oxidation step is typically performed to form a thin layer of oxide on the sides of the gate structures, which resists damage to the gate structures during the phosphoric acid strip.
One difficulty with a poly-reoxidation step to form an oxide layer on the side of the gate structures is that polysilicon re-oxidation is performed at an elevated temperature that increases the thermal budget of processing. It is desirable to reduce the overall thermal budget to reduce the tendency for diffusion of materials in active regions of the integrated circuit.
Another difficulty is that the oxide formed on the sides of the gate structures during the polysilicon re-oxidation is not localized on the sides of the gate structures, but extends to a point near the thin gate oxide layer underlying the gate conductor material. The newly-formed oxide may encroach into the gate oxide layer, which may adversely increase the thickness of the gate oxide or reduce the shape definition of the corner between the gate structure and the underlying substrate. Thus, the polysilicon re-oxidation may affect the precision with which gate structures may be formed.
Thus, there is a need to form structures in an integrated circuit using an improved method that produces structures having reduced critical dimensions. Further, there is a need to form gate structures that are not damaged by the removal of mask layers used to form the gate structures. Even further, there is a need to use amorphous carbon as a mask in the formation of integrated circuit structures. Even further still, there is a need to form gate structures without the use of a polysilicon re-oxidation process that may result in damage to the gate oxide and adversely affect definition of the gate structure. Yet further still, there is a need for a method of producing integrated circuit gate structures that does not increase the thermal budget of processing and that does not damage gate structures during processing.